1. Field of Invention
A semiconductor tester and in particular a built-off self test (BOST) for an embedded memory in a device operating simultaneous to other testing being performed.
2. Description of Related Art
Built in self test (BIST) capability occupies valuable real estate on a semiconductor chip especially for implementing a memory BIST. Economics is a prime consideration for semiconductor LCD (liquid crystal display) driver devices. Not only is the real estate that would be occupied with a BIST circuit costly, but also the need to have a tester to perform a set of tests on a semiconductor chip with a diverse set of circuitry is also costly. Testing of such a device requires a sequential set of test procedures in which the testing of the embedded memory occupies a substantial portion of the total test time. Finding ways to reduce the total test time of a device with such a diverse set of requirements is important to the reduction of total product cost.
U.S. Pat. No. 6,829,728 (Cheng et al.) is directed to a test circuit for testing embedded synchronous memories where a BIST (built-in self test) controller is used to address the memory and provide reference data to compare to the memory output. U.S. Pat. No. 6,721,904 (Ernst et al.) is directed to a BOST (built off (chip) self test) function located between a DUT (device under test) and a semiconductor tester for the purpose of testing a SDRAM. U.S. Pat. No. 6,653,855 (Mori et al.) is directed to a BOST board containing a connector, a substrate and an external self test circuit. In U.S. Pat. No. 6,587,979 (Kraus et al.) a flexible BIST is directed to being incorporated into an integrated circuit chip. In U.S. Pat. No. 6,286,115 (Stubbs) discloses a test circuit is directed an on-chip test circuit that includes a multiplexer and an interface to I/O to allow interfacing with I/O associated an embedded memory to allow testing and repairing the embedded memory. U.S. Pat. No. 6,182,257 (Gillingham) is directed to a semiconductor device with a self test circuit, which includes a test memory array, a self test controller for internally generating test and results data, and an interface for loading test data into the test memory array. U.S. Pat. No. 6,072,737 (Morgan et al.) is directed to an embedded test circuit to test an embedded DRAM of an integrated circuit chip wherein the test circuitry interfaces with a memory tester. In U.S. Pat. No. 4,873,705 (Johnson) a method and system is directed to functionally testing memories in microprocessor based units or boards under test with an interface circuit coupled to the bus structure of the unit under test.
In FIG. 1 is a diagram of prior art showing a test time sequence for testing an LCD driver chip as might be performed by automatic test equipment (ATE). DC tests are first performed as an initial screen of the chip to determine the ability of the chip to be powered and have I/O circuits free of shorts and opens. A test is then performed on the embedded array (RAM) to determine the capability of the array to properly store and read data This is then followed by analog tests to test the ability of the I/O drivers and receivers to function properly, followed by a test of the digital circuits and the chips video capability.
A built-in-self-test (BIST) circuit could be useful in reducing the test time required by an ATE particularly with respect to the embedded memory, but this would be at the cost of the additional chip size required to accommodate the BIST circuitry and the BIST would require testing. A built-off-(chip)-self test (BOST) could also be used, but an allocation of test time is still required for the embedded memory.